With the explosive growth of the cellular phone industry, the need has arisen to reduce cost and power consumption of mobile handsets. To keep costs down, the entire radio, including memory, application processor, digital baseband processor, analog baseband and RF circuits, would ideally be all integrated onto a single silicon die with a minimal count of external components. The use of low-voltage deep submicron CMOS processes allows for an unprecedented degree of scaling and integration in digital circuitry, but complicates implementation of traditional RF circuits. Furthermore, any mask adders for RF/analog circuits are not acceptable from a fabrication cost standpoint.
Consequently, a strong incentive has arisen to find digital architectural solutions to the RF functions. Areas currently in focus are phase/frequency and amplitude modulations of an RF carrier realized using a digitally-controlled oscillator (DCO) and a digitally-controlled power amplifier (DPA) circuits, respectively. They are digitally-intensive equivalents of the conventional voltage-controlled oscillator (VCO) and power amplifier (PA) driver circuits. Due to the fine feature size and high switching speed of the modern CMOS technology, the respective digital-to-frequency conversion (DFC) and digital-to-RF-amplitude conversion (DRAC) transfer functions could be made very linear and of high dynamic range.
A block diagram illustrating an example prior art polar transmitter is shown in FIG. 1. The polar transmitter, generally referenced 10, comprises CORDIC and polar signal processing block 12, digital to frequency conversion block (DFC) 14 and Digital to RF amplitude conversion block (DRAC) 16. The DFC 14 comprises a modulator 22 and digitally controlled oscillator (DCO) 24. The DRAC 16 comprises a modulator 18 and digital power amplifier (DPA) 20.
The I and Q samples of the Cartesian coordinate system generated in a digital baseband (DBB) are converted through CORDIC algorithm 12 into amplitude and phase samples of the polar coordinate system. The phase is then differentiated to obtain frequency deviation. The polar signals are then conditioned through signal processing to sufficiently increase the sampling rate in order to reduce the quantization noise density and lessen the effects of the modulating spectrum replicas. The frequency deviation output signal is fed into the DCO based DFC 14, which produces a phase modulated (PM) digital carrieryPM(t)=sgn(cos(ω0t+θ[k]))  (1)where
sgn(x)=1 for x≧0;
sgn(x)=−1 for x<0;
ω0=2πf0 is the angular RF carrier frequency;
θ[k] is the modulating baseband phase of the kth sample.
The phase
      θ    ⁡          (      t      )        =            ∫              -        ∞            t        ⁢                  f        ⁡                  (          t          )                    ⁢                          ⁢              ⅆ        t            is an integral of frequency deviation, where t=k·T0 with T0 being the sampling period.
The amplitude modulation (AM) signal controls the envelope of the phase-modulated carrier by means of the DPA based DRAC 16. Higher-order harmonics of the digital carrier are filtered out by a matching network so that the sgn( ) operator is dropped. The composite DPA output comprises the desired RF output spectrum.yRF(t)=a[k]·cos(ω0t+θ[k])  (2)where, a[k] is the modulating baseband amplitude of the kth sample.
While digital polar modulated transmitters have been demonstrated for GSM, GPRS, EDGE (GGE), their usage for 3G (WCDMA) and other wideband wireless standards remains a daunting task. Polar modulation relies on splitting the digital IQ baseband signal into a phase (i.e. frequency) and amplitude data stream. The phase signal θ (or differentiated phase signal (f=Δθ/Δt)) is used to directly modulate a digitally controlled oscillator (DCO), the output of which is then combined with the amplitude signal ρ in a Digital Power Amplifier (DPA). The θ (or f=Δθ/Δt) component generated when passing the 3.96 MHz WCDMA IQ signal through a CORDIC spreads significantly due to the nonlinear (i.e. arctan) operation. The resulting signal is no longer band limited and thus theoretically infinite modulation of the oscillator is needed to represent this phase signal. Although, in a discrete time system such as this, the maximum frequency deviation (Δf) will be limited to the sampling rate, it is still in the order of tens of MHz as shown in FIG. 2. Any truncation in phase data will degrade EVM. Tight modulation resolution has to be maintained in order to keep the frequency quantization noise much lower than electronic DCO phase noise.
Statistically, it can be shown that most of this signal can be represented in a bandwidth that is 10 times the signal bandwidth. This bandwidth, however, might be too large for a single oscillator (i.e. the DCO) to handle while still providing the needed granularity (i.e. quantization step size, phase noise, etc.) and frequency coverage to span all frequency bands, including the typical bands of GSM-EU, GSM-US, PCS, DCS and IMT2K. Since the DCO modulation range is limited, frequency data is truncated resulting in a severely degraded error vector magnitude (EVM).
This is further exacerbated by the fact that the DCO typically operates at 2× (for high frequency bands) or 4× (for low frequency bands) the actual desired output channel frequency. This implies that the DCO modulation range must be at least 4× the needed range. In practice, however, the modulation range must be even greater in order to compensate for coarse tuning step size, process, voltage and temperature (PVT) variations, etc.
Since the bandwidth requirements for existing GGE (i.e. 2 G and 2.5 G) polar transmitters are much smaller than that required for WCDMA and can thus be easily handled by the DCO. Therefore, one possible solution to the bandwidth problem described above, is to use multiple DCO circuits, one for each frequency band, corresponding to four DCO circuits. A disadvantage of this solution is that since the DCO circuit incorporates a large monolithic inductor, significant area would be consumed. Even if such a solution was constructed, it is not certain whether (1) the full modulation range (i.e. fine frequency step) could be achieved while keeping the DCO phase noise within specification or (2) whether the EVM would be degraded and compromised.
Generally, a polar modulator exhibits lower noise than a Cartesian modulator. In a polar modulator, the baseband IQ data is converted to a polar representation consisting of amplitude and phase. In such a conversion, the limited bandwidth IQ data may result in an infinite (or very large) bandwidth of the resulting phase as the IQ trajectory passes through or very close to the origin, which is the case in WCDMA modulation, for example.
A plot illustrating the IQ data sample constellation at the chip rate at the input to the TX signal processing path is shown in FIG. 3. Note that there is no chip value at zero. In addition, the constellation resembles the constellation for 8-PSK modulation. The lines indicate the connecting lines between each chip. A plot illustrating example IQ upsampled data as generated in the DTX path is shown in FIG. 4. Note that virtually all the data samples points are not at or near the origin. A graph illustrating the same IQ data as in FIG. 4 but with lines enabled showing the transition trajectory between IQ samples is shown in FIG. 5. In this plot, however, the trajectory of the IQ data samples does cross the origin as indicated by the large number of transitions through or near the origin. It is these zero crossing transitions which cause an increase in the modulation bandwidth. Such a high (possibly infinite) phase bandwidth makes it difficult and impractical to implement a polar modulator because it requires a very fast change of the oscillator phase (i.e. very wide frequency modulation of the oscillator).
Another prior art solution for reducing the phase modulation bandwidth is to use a LO exception handling mechanism such as shown in FIG. 6. A detailed description of the exception handling mechanism can be found in U.S. Publication No. 2006/0038710, to Staszewski et al., entitled “Hybrid Polar/Cartesian Digital Modulator” and in U.S. Publication No. 2008/0002788, to Akhtar et al., entitled “Local Oscillator Incorporating Phase Command Exception Handling Utilizing A Quadrature Switch,” both of which are incorporated herein by reference in their entirety.
Although the frequency control of the DCO 24 (FIG. 1) for polar modulation is extremely precise, practically it has a limited range of perhaps 10 MHz. This is disadvantageous when, during the complex modulation, the I/Q vector is close to the origin (i.e. small amplitude) and makes fast, large phase/frequency changes, such as indicated by the example trajectories in FIG. 5 as it passes near and through the origin, versus small phase/frequency changes which occur relatively far from the origin. The frequency deviation Δf requirements for WCDMA, for example, are relatively high. Unlike with EDGE, where the data rate is approximately 270 ksymbols/sec, the data rate and bandwidth in WCDMA are an order of magnitude higher. A polar architecture that may be suitable for EDGE transmission may not be readily used for certain modulation schemes such as those used in WCDMA and WLAN transmission because the modulation data rate is very high in these schemes with the resultant difficulty of performing high frequency modulation of the DCO and the amplitude.
Digital I/Q modulation, on the other hand, has the same disadvantages of the amplitude modulation part of polar transmission, and has I and Q summed together without the benefits of the fine frequency resolution of the polar modulator. Consequently, a quadrature structure of comparable resolution would be noisier. Additionally, the phase and amplitude mismatch of the I and Q paths can result in a severe distortion of the modulated signal when the two paths are finally recombined. In that sense, the polar structure is advantageous as it is insensitive to gain inaccuracies in the amplitude path and relatively easily achieves high accuracy in the phase/frequency path. The advantages of frequency modulation, namely a very fine step size of frequency control, however, becomes a disadvantage in cases where large frequency deviations are required to be performed (see FIG. 2).
A Cartesian modulator, however, operates in the I/Q domain and can change phase instantly (e.g., within one clock cycle), so it does not suffer this limitation. Note that with digital I/Q modulation, the I and Q quadrature components are regulated digitally in an open loop system and thus typically suffer dynamic-range/accuracy limitations. This limits the accuracy in the phase domain compared to what is achievable in a polar structure where a closed loop system is used to achieve very fine frequency resolution.
The prior art structure of FIG. 6 combines the advantages of both polar and Cartesian modulation structures and avoids their disadvantages. The technique utilizes a combination of an all digital phase locked loop (ADPLL) that features a wideband frequency modulation capability and a digitally controlled power amplifier (DPA) performs interpolation between 90 degree spaced quadrature phases. In operation, the phase can be changed by a multiple of 90 degrees within one clock cycle depending on the instantaneous value of the phase change. An alternative to monitoring the large instantaneous frequency deviation is to examine the small instantaneous amplitude value, since they are highly correlated. These two statistics, however, require conversion of the quadrature I/Q signals to the polar ρ/θ domain. A simple ABS(I)+ABS(Q) metric will also work well as a proxy for the amplitude and frequency deviation.
Referring to FIG. 6, the circuit, generally referenced 170, comprises an exception handler block 172, DCO 174, quadrature divide by two/four 176 and quadrature switch or multiplexer 180. In operation, the oscillator tuning word (OTW) (or frequency tuning word (FTW)) is input to the exception handler 172. The exception handler either passes the OTW through to the DCO or replaces it with a residue tuning command. The DCO generates an RF signal having a frequency in accordance with the output of the exception handler. Normally, the quad band DCO is modulated by the oscillator tuning word data stream to generate the phase (frequency) information for the DPA. In this case, however, the OTW is input to the exception handler and the output of the exception handler is used to modulate the DCO. The DCO operates at twice (IMT2K, PCS, DCS) or four times (US-cellular, EU-cellular) the band frequency. This provides the needed tuning range to permit a single oscillator span all bands while providing acceptable phase noise. The output of the DCO is passed through a quadrature generating divider 176. Typical differential dividers provide a quadrature output by default wherein only a single phase pair is (i.e. 0 and 180 degrees) is sent to the next stage (i.e. the digital pre-power amplifier or DPA).
The frequency divider is operative to output four quadrature phases. The four phases may comprise any desired phases, 0, 45, 90, etc. Here, the four phase comprise 0/180 degrees (I+/I−) and 90/270 degrees (Q+/Q−). These four outputs of the divider are input to a fast quadrature switch that functions to select between four different quadrature phase pairs based on a switch control signal 182 generated and output of the exception handler 172. The four phase pairs comprise 0/180 degrees (I+/I−), 180/0 degrees (I−/I+), 90/270 degrees (Q+/Q−) and 270/90 degrees (Q−/Q+).
The switch is implemented by passing all four quadrature outputs of the divider through four switched inverter buffers in pairs that are 180 degrees out of phase with each other. Any phase combination can then be selected by either turning on or off any two of the inverter pairs. When the DCO is commanded to modulate beyond its range (as a result of the incoming WCDMA phase data stream), the quadrature switch is enabled and a discrete jump in phase (referred to as a phase jump) is activated.
The remaining phase modulation is referred to as the residue (or correction) phase modulation and is defined as the difference between the requested phase (e.g., OTW or FTW) and the phase jump (e.g., 90 degrees). This residue phase modulation constitutes the modified or new frequency command that is input to the DCO. The phase jump combined with the residue phase command (or correction), effectively results in the original frequency request (OTW or FTW). In addition, both the phase jump and the residue correction occur and are applied simultaneously thus resulting in the signal output of the quadrature switch to contain the full requested phase modulation. Thus, the error vector magnitude (EVM) specification is met and not degraded.
A limitation with using an analog quad-switch at the output of the DCO to achieve fast phase modulation is that the analog quad-switch can only achieve +/−90 to +/−180 degree phase jumps. Thus, any residue phase must be compensated with the DCO frequency modulation, which suffers from phase discontinuity and excessive phase noise. A graph illustrating the phase discontinuity resulting from the use of the prior art local oscillator exception handling mechanism of FIG. 6 is shown in FIG. 7 wherein trace 196 represents the reference signal and trace 194 represents the signal resulting from the prior art local oscillator exception handling mechanism. In addition, the analog quad-switch also requires calibration and compensation so that the switching control can be matched with the frequency modulation.
It is thus desirable to have a mechanism that overcomes the disadvantage of the prior art techniques. The mechanism should preferably be implementable as a simple, all digital implementation and be capable of enabling a polar transmitter to be used with wideband modulation schemes. More specifically, the mechanism should enable an oscillator having a limited bandwidth to be used with large modulation ranges required by wideband modulation schemes such as 3G WCDMA.